1. Technical Field
The present disclosure relates to nonvolatile memory architectures. In particular, the disclosure relates to the architecture of an Electrically Erasable and Programmable Read-Only Memory (EEPROM).
2. Description of the Related Art
Nonvolatile memories (NVM) allow data to be stored even when no power is applied. Conventional Electrically Erasable and Programmable memories are generally classified into two categories: EEPROMs on the one hand, and Flash-EEPROM or “Flash” memories on the other hand.
Memory cells of conventional EEPROMs comprise a floating-gate transistor and a selection transistor. The selection transistor has a control gate terminal connected to a word line, a first conduction terminal connected to a bit line and a second conduction terminal connected to a first conduction terminal of the floating gate transistor. The floating gate transistor has a control gate terminal connected to a control gate line.
Memory cells of conventional Flash memories only comprise a floating gate transistor that has a control gate connected to a word line and a first conduction terminal connected to a bit line.
It is well known that EEPROM memory cells are suitable to realize word-erasable memories. Conventionally, a “word” comprises a group of N memory cells whose floating gate transistors are connected to a common control gate line. The control gate line is linked to a column latch that allows an erase voltage to be simultaneously applied to all the control gate terminals of the floating gate transistors of the word. Memory cells belonging to other words of the memory have the control gate terminals of their floating gate transistors controlled by other control gate lines and column latches.
It is also well known that Flash memory cells are suitable to realize page-erasable memories, a “page” comprising all the memory cells of a row, since the control gate terminals of the memory cells of a row are interconnected and receive the same erase voltage.
Therefore, EEPROMs are generally used in applications where word-erasability is sought, while Flash memories are generally used in applications where high density is sought and word-erasability is not necessary. For example, EEPROMs are often used to store application data while Flash memories are used to store code (program data).
Another difference between EEPROM memories and Flash memories resides in the arrangement of the data within a row.
EEPROM memories generally comprise rows of memory cells in which data is stored in a manner corresponding to the logical architecture of the memory. For example, assuming that a row of the memory is designed to store M words W0-WM-1, each comprising N bits B0-BN-1, bits B0-BN-1 of the word W0 are stored in a first column C0, bits B0-BN-1 of the word W1 are stored in a second column C1, etc., and bits B0-BN-1 of the word WM-1 are stored in the last column CM-1 of the memory.
On the contrary, in a row of a Flash memory, all bits of same rank belonging to different words are generally stored in memory cells that are adjacent and belong to a same column. For example, assuming again that a row is designed to store M words W0-WM-1 and that each word comprises N bits B0-BN-1, all bits B0 of the same rank 0 of words W0-WM-1 of the row are stored in a first column C0, all bits B1 of the same rank 1 of words W0-WM-1 are stored in a second column C1, etc. and all bits BN-1 of the same rank N-1 of words W0-WM-1 are stored in the last column CN-1 of the memory.
To summarize, a memory comprising rows of M words of N bits may comprise M columns of N memory cells and N bit lines if it is a EEPROM memory, and may comprise N columns of M memory cells and M bit lines if it is a Flash memory.
This difference in architecture has an effect upon the connection of the bit lines to sense amplifiers provided to read the memory cells. No matter which type of memory architecture is used, each sense amplifier is generally dedicated to the reading of bits having the same rank, and the number of sense amplifiers is equal to the number of bits in a word.
If a memory with M words per row and N bits per word is realized according to the EEPROM architecture, the first sense amplifier SA0 is connected to a first bit line BL0 of the first column C0, to a first bit line BL0 of column C1, etc., and to a first bit line BL0 of the last column CM-1. Likewise, the second sense amplifier SA1 is connected to a second bit line BL1 of column C0, to a second bit line BL1 of column C1, etc., and to a second bit line BL1 of the last column CM-1, etc. The last sense amplifier SAN-1 is connected to a last bit line BLN-1 of column C0, to a last bit line BLN-1 of column C1, etc., and to a last bit line BLN-1 of the last column CM-1.
If such a memory is realized according to the Flash architecture, a first sense amplifier SA0 is connected to the M adjacent bit lines of the first column C0, a second sense amplifier SA1 is connected to the M adjacent bit lines of the second column C1, etc., and a Nth sense amplifier SAN-1 is connected to the M adjacent bit lines of the last column CN-1.
Since the connection of the sense amplifiers to the bit lines is done through multiplexing lines, the length of the multiplexing lines is generally approximately equal to the width of the memory array in an EEPROM memory whereas in a Flash memory, it is approximately equal to the width of a column. Now, the longer a multiplexing line is, the greater a corresponding parasitic capacitance is, resulting in longer read access times and higher electrical consumption due to longer pre-charge periods and capacitance value.
Finally, since bits of the same word are stored in memory cells connected to adjacent bit lines in an EEPROM memory and are read simultaneously by the sense amplifiers, crosstalk may occur between the bit lines during a read operation.
Therefore, it is apparent that Flash architectures and EEPROM architectures have respective advantages and disadvantages that can be summarized as follows:
FLASHEEPROMSense amplifiers S0-SN−1 readSense amplifiers S0-SN−1 read bitsbits B0-BN−1 of a word byB0-BN−1 of a word by means of adjacentmeans of non-adjacent bit linesbit linesShort multiplexing lines toLong multiplexing lines to interconnectinterconnect bit lines and sensebit lines and sense amplifiersamplifiersLower parasitic capacitanceHigher parasitic capacitanceLower electrical consumptionHigher electrical consumption duringduring read cycle due to lowerread cycle due to higher parasiticparasitic capacitancecapacitanceShorter access timeLonger access timeNo crosstalk or low crosstalkHigher crosstalkPage erasableWord erasableHigher density (one transistorLower density (two transistors perper memory cell)memory cell)
So-called “embedded memories” are memories embedded within an integrated circuit comprising further components. For example, an integrated circuit for chip card may contain a microcontroller, I/O circuitry and an embedded memory. In such embedded memory applications, it is generally desired that the embedded memory can be used both to store program data and application data, to avoid having to provide two different memories, one to store program data and the one other to store application data. For this reason, embedded memories must address different contradictory needs. For example, an embedded conventional EEPROM is convenient to store data but offers mediocre electrical consumption efficiency when data are read, due to the parasitic capacitance of the multiplexing lines.
Therefore, it may be desired to provide a memory architecture optimized for embedded memory applications.